The present invention relates to a semiconductor device such as a ferroelectric memory cell, a DRAM, and the like and a method of producing the semiconductor device, and more particularly, to a method of forming a microscale capacitor for such a semiconductor device.
As the semiconductor device, a ferroelectric memory cell having a one-transistor/one-capacitor structure is known. In the ferroelectric memory cell, a planar capacitor is formed over a transistor with an insulating film interposed therebetween. The transistor and the capacitor are completely isolated from each other. Therefore, after the capacitor is formed on the insulating film, the transistor and the capacitor are connected to each other locally with wiring. However, the memory cell with this structure occupies a large area and is unsuitable for achieving high packing densities or integration.
To solve the problem, there has been proposed a ferroelectric memory cell having a structure as shown in FIG. 3 in which a plug 102 made of polysilicon or TaSiN is formed on a source region 101 of a MOSFET 110 and a stacked capacitor is formed over the plug 102. In FIG. 3, reference numeral 103 denotes a barrier metal formed on the plug 102. Reference numeral 104 denotes a lower electrode, reference numeral 105 denotes a ferroelectric film, reference numeral 106 denotes an upper electrode, reference numeral 107 denotes a drive line, and reference numeral 111 denotes a metal wiring.
In the structure of the ferroelectric memory cell shown in FIG. 3, flat films to become the lower electrode 104, the ferroelectric film 105, and the upper electrode 106 are sequentially stacked on the plug 102 and an insulating film 100 and etched altogether to form a capacitor. The effective area of the capacitor is limited to the area of a flat part. Therefore, the ferroelectric memory cell is incapable of having a sufficient capacitor area if the memory cell has an area as small as less than a quarter micron.
As a solution to the above problem, as shown in FIG. 4, there has been provided a structure for a ferroelectric memory cell and a DRAM in which a plug 204 of polysilicon or tungsten is formed on a source region 201 of a MOSFET 210 formed on a silicon substrate 200, and a stacked capacitor Cp is formed on the plug 204.
The stacked capacitor structure shown in FIG. 4 is formed by the following method on a semiconductor substrate formed with a MOSFET 210, interlayer insulating films 202 and 203 on the MOSFET 210, and a plug 204 in a contact hole 202a of the interlayer insulating films 202 and 203. A conductive film of Ir, IrO2/Ir, Pt, Ru, or RuO2/Ru is deposited on the plug 204 and then patterned by dry etching to form a lower electrode 205 (node electrode). Thereafter, a ferroelectric (e.g., PZT: lead zirconate titanate, SBT: strontium bismuth tantalate) or a high dielectric constant film (e.g., BST: barium strontium titanate) is deposited so as to cover the lower electrode 205. Then, a conductive film of Ir, IrO2, Pt, Ru, or RuO2, which will become an upper electrode, is deposited on the ferroelectric or high dielectric constant film. Thereafter, the conductive film and the ferroelectric film (or the high-dielectric-constant film) are patterned by the dry etching to form a common plate (or a drive line) consisting of the lower electrode 205, the ferroelectric (or high dielectric constant) film 206, and the upper electrode 206.
In the above stacked capacitor structure, if the lower electrode 205 is formed to be large in thickness to increase the area of the capacitor, then the etching process takes long because of a low etching rate proper to the dry etching method. Further, the conductive film made of Pt, Ir or IrO2, which is used to form the lower electrode 205 or the upper electrode 207, has a low reactivity with a halogenating gas ordinarily used in the dry etching process. Further, because its reaction product has a low volatility, the etching rate of the conductive film is low. Thus the stacked capacitor structure has a problem that it is difficult to perform micro-processing. The stacked capacitor structure has another problem that because the influence of a micro-loading effect is great in the case of a pattern of the order of less than submicron, the reaction product adheres to the conductive film and particles are developed on the conductive film.
To solve the problem, Sharp K. K. has proposed a semiconductor device with a three-dimensional capacitor structure capable of increasing the effective capacitor area (Japanese Patent Application Laid-open No. 2000-196039). This semiconductor device will be described below merely for the better understanding of the present invention although it is not a prior art to the present invention.
In producing the semiconductor device having the three-dimensional capacitor structure, as shown in FIG. 5, a plug 302 is formed in an interlayer insulating film 300 formed on a source region 301, and a buried barrier metal 303 is formed on the plug 302. After the plug 302 with buried barrier metal 303 was formed, an insulating film 310 is deposited and then grooved at 310a. Then, an electrode film is deposited on the insulating film 310 including inside of the groove 310a and then processed by the chemical mechanical polishing (CMP) method to thereby form a capacitor lower electrode 304. With this method of producing the semiconductor device, even side surfaces of the lower electrode 304 are used as part of a capacitor. Thus the capacitor has an increased area. But according to the three-dimensional capacitor structure shown in FIG. 5, with reduction of the design rule, the groove is made finer. Accordingly, it will be difficult to form the lower electrode, the ferroelectric film, and the upper electrode within the groove.